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2200 mhz to 2700 mhz balanced mixer, lo buffer, if amplifier, and rf balun ADL5353 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is gra nted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. features f requency range s of 22 00 mhz to 2700 mhz (rf) and 3 0 mhz to 450 mhz (if) power conversion gain: 8. 7 db input ip3 of 24.5 dbm and i nput p1db of 10. 4 dbm ssb noise figure of 9. 8 db typical lo d rive of 0 dbm single - ended, 50 ? rf and lo input ports high i solation spdt lo input switch single -s upply o peration: 3.3 v to 5 v exposed pad, 5 mm 5 mm 20 -l ead lfcsp 1500 v hbm/500 v ficdm esd p erformance applications cellular base station receivers transmit observation receivers radio link downconverters ge neral description the ADL5353 us es a highly linear , doubly balanced passive mixer core along with integrated rf and local oscillator ( lo ) balancing circuitry to allow for single - ended operation. the ADL5353 incorporates an rf balun to provide optimal perf or- mance over a 22 00 mhz to 2700 mhz input frequency range using high - side lo . the balanced passive mixer arrangement provides good lo - to - rf leakage, typically better than ?36 dbm, and excellent intermodulation performance. the balanced mixer core also pr ovides extremely high input linearity , allowing the device to be used in demanding cellular applications where in - band blocking signals m ight otherwise result in the degrada tion of d ynamic performance. a high linearity if buffer amp lifier follows the pass ive mixer core to yield a typical power conversion gain of 8. 8 db and can be us ed with a wide range of output impedances. functional block dia gram 2 3 1 20 19 18 17 16 6 7 8 9 10 4 5 14 13 15 12 bias generator vpif rfin rfct comm comm loi2 vpsw vgs1 vgs0 loi1 ifgm ifop ifon pwdn lext vlo3 lgm3 vlo2 losw nc ADL5353 nc = no connect 11 09117-001 figure 1. the ADL5353 provides two switched lo paths that can be us ed in tdd a pp lications where it is desirable to rapidly switch between two local oscillators. lo current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. for low voltage applications, the ADL5353 is capab le o f operation at voltages down to 3.3 v with substantially reduced current. for low voltage operation, an additional logic p in is provided to power down (<2 00 a) the circuit when desired. the ADL5353 is fabricated using a bicmos high performance ic pro c ess. the device is available in a 5 mm 5 mm, 20- lead lfcsp and operates over a ? 40c to +85c temperature range. an evaluation board is also available. table 1 . passive mixers rf frequency (mhz) single mixer single mixer and if am p dual mixer and if amp 500 to 1700 adl5367 adl5357 adl5358 1200 to 2500 adl5365 adl5355 adl5356 22 00 to 27 00 ADL5353 adl53 54
ADL5353 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? 5 v performance specifications .................................................. 3 ? 3.3 v performance specifications ............................................... 4 ? absolute maximum ratings ............................................................ 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? 5 v performance ........................................................................... 7 ? 3.3 v performance ...................................................................... 14 ? spur tables ...................................................................................... 15 ? circuit description......................................................................... 16 ? rf subsystem .............................................................................. 16 ? lo subsystem ............................................................................. 16 ? applications information .............................................................. 18 ? basic connections ...................................................................... 18 ? bias resistor selection ............................................................... 18 ? mixer vgs control dac .......................................................... 18 ? evaluation board ............................................................................ 19 ? outline dimensions ....................................................................... 22 ? ordering guide .......................................................................... 22 ? revision history 10/10revision 0: initial version
ADL5353 rev. 0 | page 3 of 24 specifications 5 v pe r formance specifications rf interface v s = 5 v, i s = 190 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, l o power = 0 dbm, z o = 50 ?, unless otherwise noted. table 2 . parameter test conditions /comments min typ max unit rf input interface return loss tunable to >20 db over a limited bandwidth 18 db input impedance 50 ? rf frequency range 2200 27 00 mhz output interface output impedance differential impedance, f = 200 mhz 230|| 1.5 ?| |pf if frequency range 30 450 mhz dc bias voltage 1 externally generated 3.3 5.0 5. 5 v lo interface lo power ?6 0 + 10 dbm return loss 15 db input impedance 50 ? lo frequency range 22 30 3150 mhz power - down (pwdn) interface 2 pwdn threshold 1.0 v logic 0 level 0.4 v logic 1 level 1.4 v pwdn response time device enabled, if o utput to 90% of its final level 160 ns device d isabled, supply current < 5 ma 220 n s pwdn input bias current device enabled 0.0 a device disabled 70 a 1 apply the s upply voltage from the external circuit through the choke inductors . 2 the power - down function is intended for use with v s 3.6 v only.
ADL5353 rev. 0 | page 4 of 24 rf dynamic performance v s = 5 v , i s = 190 ma , t a = 25 c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, vgs0 = vgs1 = 0 v, a n d z o = 50 ?, unless otherwise noted. table 3 . parameter test conditions /comments min typ max unit dynamic performance power conversion gain including 4:1 if port transformer and pcb loss 8. 7 db voltage conversion gain z source = 50 ? , d ifferential z load = 200 ? d ifferential 14. 7 db ssb noise figure 9. 8 db input thir d- order intercept (i ip3) f rf1 = 2534.5 mhz, f rf2 = 2535.5 mhz, f lo = 2738 mhz, each rf tone at ? 10 dbm 21 2 4.5 dbm input second - order intercept (i ip2) f rf 1 = 2535 mhz, f rf2 = 2585 mhz, f lo = 2738 mhz, each rf tone at ? 10 dbm 4 7.5 dbm input 1 db compression point (i p1db) 10. 4 dbm lo -to - if leakage unfiltered if o utput ?15 dbm lo -to - rf leakage ?38 dbm rf -to- if isolation ? 28 db c if/2 spurious ? 10 dbm input power ? 70 dbc if/3 spurious ? 10 dbm input power ?78 dbc power supply positive supply voltage 4.5 5.0 5.5 v quiescent current lo supply, resistor programmable 100 ma if supply, resistor programmable 90 ma total quiesc ent current v s = 5 v 1 90 ma 3.3 v performance specifications v s = 3.3 v, i s = 125 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, r9 = 226 , r14 = 604 , vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. table 4. parameter test conditions /comments min typ max unit dynamic performance power conversion gain including 4:1 if port transformer and pcb loss 9 db voltage conversion gain z source = 50 ? , differential z load = 200 ? differentia l 15 db ssb noise figure 8.95 db input third - order intercept (iip3) f rf1 = 2534 .5 mhz, f rf2 = 2535 .5 mhz, f lo = 2738 mhz, each rf tone at ?10 dbm 19 dbm input second - order intercept (iip2) f rf1 = 2535 mhz, f rf2 = 2 5 85 mhz, f lo = 2738 mhz , each rf tone at ?10 dbm 41.5 dbm input 1 db compression point (ip1db) 7.5 dbm power interface supply voltage 3.0 3.3 3.6 v quiescent current resistor programmable 125 ma power - down current device disabled 150 a
ADL5353 rev. 0 | page 5 of 24 absolu te maximum ratings table 5 . parameter rating supply voltage, v s 5.5 v rf input level 20 dbm lo input level 13 dbm if op , if on bias voltage 6 .0 v vgs0, vgs1, losw, pwdn 5.5 v internal power dissipation 1.2 w thermal resi stance , ja 25 c/w temperature maximum junction temperature 150c operating temperature range ? 40c to + 85c storage temperature range ?65c to +150c lead temperature (soldering , 60 sec) 260c stresses above those listed under absolute maximum rating s may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximu m rating conditions for extended periods may affect device reliability. esd caution
ADL5353 rev. 0 | page 6 of 24 pin configuration and function descripti ons pin 1 indicator notes 1. nc = no connect. 2. exposed pad. must be soldered to ground. 1vpif 2 rfin 3 rfct 4 comm 5 comm 13 vgs1 14 vpsw 15 loi2 12 vgs0 11 loi1 6 vlo3 7 lgm3 8 vlo2 10nc 9 losw 18 ifon 19 ifop 20 ifgm 17 pw dn 16 l ext top view (not to scale) ADL5353 09117-002 figure 2. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 vpif positive supply voltage for if amplifier . 2 rfin rf input. must be ac - coupled. 3 rfct rf balun center tap (ac ground). 4, 5 comm device common (dc ground). 6, 8 vlo3, vlo2 positive supply voltage s for lo amplifier. 7 lgm3 lo amplifier bias control. 9 losw lo switch. loi1 selected for 0 v, and loi2 selected for 3 v. 10 nc no connect. 11, 15 loi1, loi2 lo input s . must be ac - coupled. 12, 13 vgs0, vgs1 mixer gate bias control s. 3 v logic. ground these pins for nomina l setting . 14 vpsw positive supply voltage for lo switch. 16 lext if return . this pin must be grounded. 17 pwdn power down. connect this pin to ground for normal operation and c onnect this pin to 3. 0 v for disable mode. 18, 19 ifon, ifop differential i f o utput s (open collectors). each requires an external dc bias. 20 ifgm if amplifier bias control. epad (ep) exposed p ad. the exposed pad must be soldered to ground.
ADL5353 rev. 0 | page 7 of 24 typical performance characteristics 5 v performance v s = 5 v, i s = 190 ma, t a = 25c , f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, r9 = 1.1 k ?, r14 = 910 ?, vgs0 = vgs1 = 0 v, and z o = 50 ?, unless otherwise noted. 220 210 200 190 180 170 160 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 supply current (ma) rf frequency (ghz) t a = ?40c t a = +25c t a = +85c 09117-003 figure 3 . supply current vs. rf frequency 12 11 10 9 8 7 6 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 conversion gain (db) rf frequency (ghz) t a = ?40c t a = +25c t a = +85c 09117-004 figure 4 . power conversion gain vs. rf frequency 28 26 24 22 20 18 16 14 12 10 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 input ip3 (dbm) rf frequency (ghz) t a = ?40c t a = +25c t a = +85c 09117-005 figure 5 . input ip3 vs. rf frequency 70 60 50 40 30 20 10 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 input ip2 (dbm) rf frequency (ghz) t a = ?40c t a = +25c t a = +85c 09117-006 figure 6 . input ip2 vs. rf frequency 14 12 10 8 6 4 2 0 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 input p1db (dbm) rf frequency (ghz) t a = ?40c t a = +25c t a = +85c 09117-007 figure 7 . input p1db vs. rf frequency 12 11 10 9 8 7 6 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 ssb noise figure (db) rf frequency (ghz) t a = ?40c t a = +25c t a = +85c 09117-008 figure 8 . ssb noise figure vs. rf frequency
ADL5353 rev. 0 | page 8 of 24 v s = 5 v, i s = 190 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, r9 = 1.1 k ?, r14 = 910 ?, vgs0 = vgs1 = 0 v, and z o = 50 ?, unless otherwise noted. 240 220 200 180 160 140 120 100 ?40 80 60 40 20 0 ?20 supply current (ma) temperature (c) v s = 5.25v v s = 4.75v v s = 5.00v 09117-009 figure 9 . supply current vs. temperature 9.8 9.6 9.4 9.2 9.0 8.8 8.6 8.4 8.2 ?40 80 60 40 20 0 ?20 conversion gain (db) temperature (c) v s = 4.75v v s = 5.25v 09117-010 v s = 5.00v figure 10 . power conversion gain vs. temperature 28 27 26 25 24 23 22 21 20 ?40 80 60 40 20 0 ?20 input ip3 (dbm) temperature (c) v s = 5.00v v s = 4.75v v s = 5.25v 09117-011 figure 11 . input ip3 vs. temperature 52 51 50 49 48 47 46 45 44 ?40 80 60 40 20 0 ?20 input ip2 (dbm) temperature (c) v s = 5.00v v s = 4.75v v s = 5.25v 09117-012 figure 12 . input ip2 vs. temperature 14 13 12 11 10 9 8 7 6 5 4 ?40 80 60 40 20 0 ?20 input p1db (dbm) temperature (c) v s = 5.00v v s = 4.75v v s = 5.25v 09117-013 figure 13 . input p1db vs. temperature 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 ?40 80 60 70 40 20 0 ?20?30 50 30 10 ?10 ssb noise figure (db) temperature (c) v s = 5.00v v s = 5.25v v s = 4.75v 09117-014 figure 14 . ssb noise figure vs. temperature
ADL5353 rev. 0 | page 9 of 24 v s = 5 v, i s = 190 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo powe r = 0 dbm, r9 = 1.1 k?, r14 = 910 ?, vgs0 = vgs1 = 0 v, and z o = 50 ?, unless otherwise noted. 220 160 170 180 190 200 210 30 430 380 330 280 230 180 13080 supply current (ma) if frequency (mhz) t a = ?40c t a = +25c t a = +85c 09117-015 figure 15 . supply current vs. if frequency 12 6 7 8 9 10 11 30 430 380 330 280 230 180 13080 conversion gain (ma) if frequency (mhz) t a = ?40c t a = +25c t a = +85c 09117-016 figure 16 . power conversion gain vs. if frequency 30 28 26 24 22 20 18 16 30 430 380 330 280 230 180 13080 input ip3 (dbm) if frequency (mhz) t a = ?40c t a = +25c t a = +85c 09117-017 figur e 17 . input ip3 vs. if frequency 60 55 50 45 40 35 30 30 430 380 330 280 230 180 13080 input ip2 (dbm) if frequency (mhz) t a = ?40c t a = +25c t a = +85c 09117-018 figure 18 . input ip2 vs. if frequency 16 14 12 10 8 6 4 30 430 380 330 280 230 180 13080 input p1db (dbm) if frequency (mhz) t a = ?40c t a = +25c t a = +85c 09117-019 figure 19 . input p1db vs. if frequency 11.0 10.5 10.0 9.5 9.0 8.5 8.0 ssb noise figure (db) if frequency (mhz) 09117-020 30 430 380 330 280 230 180 13080 figure 20 . ssb noise figure vs. if frequency
ADL5353 rev. 0 | page 10 of 24 v s = 5 v, i s = 190 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo powe r = 0 dbm, r9 = 1.1 k?, r14 = 910 ?, vgs0 = vgs1 = 0 v, and z o = 50 ?, unless otherwise noted. 13 11 12 10 9 8 7 6 5 ?6 10 86420 ?2?4 conversion gain (db) lo power (dbm) t a = ?40c t a = +25c t a = +85c 09117-021 figure 21 . power conversion gain vs. lo power 30 26 28 24 22 20 18 16 14 ?6 10 86420 ?2?4 input ip3 (dbm) lo power (dbm) t a = ?40c t a = +25c t a = +85c 09117-022 figure 22 . input ip3 vs. lo power 60 55 50 45 40 35 30 ?6 10 86420 ?2?4 input ip2 (dbm) lo power (dbm) t a = ?40c t a = +25c t a = +85c 09117-023 figure 23 . input ip2 vs. lo power 14 12 13 11 10 9 8 7 6 ?6 10 86420 ?2?4 input p1db (dbm) lo power (dbm) t a = ?40c t a = +25c t a = +85c 09117-024 figure 24 . input p1db vs. lo power ?50 ?75 ?70 ?65 ?60 ?55 2.20 2. 70 2.652.602.552.502.452.402.352.302.25 if/2 spurious (dbm) rf frequency (ghz) t a = ?40c t a = +25c t a = +85c 09117-025 figure 25 . if/2 spurious vs. rf frequency, rf power = ? 10 dbm ?60 ?90 ?85 ?80 ?75 ?70 ?65 2.20 2. 70 2.652.602.552.502.452.402.352.302.25 if/3 spurious (dbc) rf frequency (ghz) t a = ?40c t a = +25c t a = +85c 09117-026 figure 26 . if/3 spurious vs. r f frequency, rf power = ? 10 dbm
ADL5353 rev. 0 | page 11 of 24 v s = 5 v, i s = 190 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, r9 = 1.1 k?, r14 = 910 ?, vgs0 = vgs1 = 0 v, and z o = 50 ?, unless otherwise noted. 100 80 60 40 20 0 8.70 8.90 8.80 8.85 8.75 distribution percentage (%) conversion gain (db) 09117-027 figure 27 . power conve rsion gain distribution 100 80 60 40 20 0 22 23 24 25 26 27 distribution percentage (%) input ip3 (dbm) 09117-028 figure 28 . input ip3 distribution 100 80 60 40 20 0 9.0 9.4 9.8 10.2 10.6 11.0 11.4 11.8 distribution percentage (%) input p1db (dbm) 09117-029 figure 29 . input p1db distribution 500 400 300 200 100 0 10 8 6 4 2 0 30 430 380 330 280 230 180 13080 resistance ( ?) capacitance (pf) if frequency (mhz) 09117-030 figure 30 . if differential output impedance (r parallel c equivalent) 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 2.20 2.702.652.602.552.502.452.402.352.302.25 rf return loss (db) rf frequency (ghz) 09117-031 figure 31 . rf port return loss, fixed if 0 ?5 ?10 ?15 ?20 ?25 ?30 2.0 3.02.92.82.72.62.52.42.32.22.1 lo return loss (db) lo frequency (ghz) selected unselected 09117-032 figure 32 . lo return loss, selected and unselected
ADL5353 rev. 0 | page 12 of 24 v s = 5 v, i s = 190 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, r9 = 1.1 k?, r14 = 910 ?, vgs0 = vgs1 = 0 v, and z o = 50 ?, unless otherwise noted. 60 30 35 40 45 50 55 2.20 2.702.652.602.552.502.452.402.352.302.25 lo switch isolation (db) lo frequency (ghz) t a = ?40c t a = +25c t a = +85c 09117-033 figure 33 . lo switch isolation vs. lo frequency ?20 ?36 ?34 ?32 ?30 ?28 ?26 ?24 ?22 2.20 2.702.652.602.552.502.452.402.352.302.25 rf-to-if isolation (dbc) rf frequency (ghz) t a = ?40c t a = +25c t a = +85c 09117-034 figure 34 . rf -to- if isolation vs. rf freq uency ?10 ?20 ?19 ?18 ?17 ?16 ?15 ?14 ?13 ?12 ?11 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.902.85 lo-to-if leakage (dbm) lo frequency (ghz) t a = ?40c t a = +25c t a = +85c 09117-035 figure 35 . lo -to- if leakage vs. lo frequency ?20 ?25 ?30 ?35 ?40 ?45 2.40 2. 45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.902.85 lo-to-rf leakage (dbm) lo frequency (ghz) t a = ?40c t a = +25c t a = +85c 09117-036 figure 36 . lo -to- rf leakages vs. lo frequency 0 ?10 ?20 ?30 ?40 ?50 ?60 2.40 2. 45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.902.85 2lo leakage (dbm) lo frequency (ghz) 2lo to rf 2lo to if 09117-037 figure 37 . 2lo leakage vs. lo frequency 0 ?5 ?10 ?15 ?20 ?25 ?30 2.40 2. 45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.902.85 3lo leakage (dbm) lo frequency (ghz) 3lo to rf 3lo to if 09117-038 figure 38 . 3lo leakage vs. lo frequency
ADL5353 rev. 0 | page 13 of 24 v s = 5 v, i s = 190 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, r9 = 1.1 k?, r14 = 910 ?, vgs0 = vgs1 = 0 v, and z o = 50 ?, unless otherwise noted. 10 0 1 2 3 4 5 6 7 8 9 15 5 6 7 8 9 10 11 12 13 14 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.702.65 conversion gain (db) ssb noise figure (db) rf frequency (ghz) vgs = 00 vgs = 01 vgs = 10 vgs = 11 09117-039 figure 39 . power conversion gain and ssb noise figure vs. rf frequency 15 8 28 14 26 13 24 12 22 11 20 10 18 9 16 14 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.702.65 input p1db (dbm) input ip3 (dbm) rf frequency (ghz) vgs = 00 vgs = 01 vgs = 10 vgs = 11 09117-040 figure 40 . input ip3 and input p1db vs. rf frequency 12 11 10 9 8 7 6 30 25 20 15 10 5 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 conversion gain and ssb noise figure (db) input ip3 (dbm) lo bias resistor value (k ?) conversion gain ssb noise figure input ip3 09117-041 figure 41 . power conversion gain, ssb noise figure , and input ip3 vs. lo bias resistor value 160 140 120 100 80 60 40 600 800 1000 1200 1400 1600 1800 supply current (ma) bias resistor value ( ?) lo supply current if supply current 09117-043 figure 42 . lo and if supply current vs. if and lo bias resistor value 12 11 10 9 8 7 6 30 25 20 15 10 5 0 0.6 0.7 0.9 1.1 1.3 1.5 0.8 1.0 1.2 1.4 1.6 conversion gain and ssb noise figure (db) input ip3 (dbm) if bias resistor value (k ?) conversion gain ssb noise figure input ip3 09117-044 figure 43 . power conversion gain, ssb noise figure , and input ip3 vs. if bias resistor value
ADL5353 rev. 0 | page 14 of 24 3.3 v performance v s = 3.3 v, i s = 125 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, r9 = 226 , r14 = 604 , vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. 138 136 134 132 130 128 126 124 supply current (ma) rf frequency (ghz) 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.702.65 t a = ?40c t a = +25c t a = +85c 09117-045 figure 44 . supply current vs. rf frequency at 3.3 v 12 11 10 9 8 7 6 conversion gain (db) rf frequency (ghz) 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.702.65 t a = ?40c t a = +25c t a = +85c 09117-046 figure 45 . power conversion gain vs. rf frequency at 3.3 v 24 20 22 18 16 14 12 10 input ip3 (dbm) rf frequency (ghz) 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.702.65 t a = ?40c t a = +25c t a = +85c 09117-047 figure 46 . input ip3 vs. rf frequency at 3.3 v 60 55 50 45 40 35 30 input ip2 (dbm) rf frequency (ghz) 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.702.65 t a = ?40c t a = +25c t a = +85c 09117-048 figure 47 . input ip2 vs. rf frequency at 3.3 v 9 7 5 8 6 4 3 2 1 0 input p1db (dbm) rf frequency (ghz) 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.702.65 t a = +25c t a = +85c t a = ?40c 09117-049 figure 48 . input p1db vs. rf frequency at 3.3 v 14 13 11 12 10 9 8 7 6 ssb noise figure (db) rf frequency (ghz) 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.702.65 t a = +25c t a = +85c t a = ?40c 09117-050 f igure 49 . ssb noise figure vs. rf frequency at 3.3 v
ADL5353 rev. 0 | page 15 of 24 spur tables spur tables all spur tables are (n f rf ) ? (m f lo ) and were measured using the standard evaluation board. mixer spurious products are measured in dbc from the if output power level. data was measured for frequencies less than 6 ghz only. typical noise floor of the measu rement system = ?100 dbm. 5 v performance v s = 5 v, i s = 190 ma, t a = 25c, f rf = 2600 mhz, f lo = 2803mhz, lo power = 0 dbm, rf power = ?10 dbm, vgs0 = vgs1 = vgs2 = 0 v, and z o = 50 , unless otherwise noted. m 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 n 0 ?14.9 ?33.1 1 ?36.5 0.00 ?63.4 ?59.8 2 ?80.2 ?87.8 ?66.8 ?86.8 3 ADL5353 rev. 0 | page 16 of 24 circuit description the ADL5353 consists of two primary components: the radio frequency (rf) subsystem and the local oscillator (lo) subsystem. the combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technolo- gies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. in addition, the need for external components is minimized, thereby optimizing cost and size. the rf subsystem consists of an integrated, low loss rf balun, passive mosfet mixer, sum termination network, and if amplifier. the lo subsystem consists of an spdt-terminated fet switch and a three stage, limiting lo amplifier. the purpose of the lo subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the lo input. a block diagram of the device is shown in figure 50. 2 3 1 20 19 18 17 16 6 7 8 9 10 4 5 14 13 15 12 bias generator vpif rfin rfct comm comm loi2 vpsw vgs1 vgs0 loi1 ifg m ifop ifon pwdn lext vlo3 lgm3 vlo2 losw nc ADL5353 nc = no connect 11 09117-149 figure 50. simplified schematic rf subsystem the single-ended, 50 rf input is internally transformed to a balanced signal using a low loss (<1 db) unbalanced-to-balanced (balun) transformer. this transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the rf port. although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. the rf balun can easily support an rf input frequency range of 2200 mhz to 2700 mhz. the resulting balanced rf signal is applied to a passive mixer that commutates the rf input with the output of the lo subsystem. the passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. the only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. because the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all the idler (m n product) frequencies generated by the mixing process. terminating the mixer avoids the generation of unwanted intermodulation pro- ducts and reduces the level of unwanted signals at the input of the if amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. this termination is accomplished by the addition of a sum network between the if amplifier and the mixer and also in the feedback elements in the if amplifier. the if amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that are required to achieve the overall performance. the balanced open-collector output of the if amplifier, with impedance mod- ified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, differential amplifier, or to an analog-to-digital input while providing optimum second- order intermodulation suppression. the differential output impedance of the if amplifier is approximately 200 . if operation in a 50 system is desired, the output can be transformed to 50 by using a 4:1 transformer. the intermodulation performance of the design is generally limited by the if amplifier. the input ip3 performance can be optimized by adjusting the if current with an external resistor. figure 41, figure 42, and figure 43 illustrate how various if and lo bias resistors affect the performance with a 5 v supply. addi- tionally, dc current can be saved by increasing either or both resistors. it is permissible to reduce the dc supply voltage to as low as 3.3 v, further reducing the dissipated power of the part. (note that no performance enhancement is obtained by reducing the value of these resistors, and excessive dc power dissipation may result.) lo subsystem the ADL5353 has two lo inputs permitting multiple synthe- sizers to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. the two inputs are applied to a high isolation spdt switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the lo sources. this multiple section switch also ensures high isolation to the off input, minimizing any leakage from the unwanted lo input that may result in undesired if responses. the single-ended lo input is converted to a fixed amplitude differential signal using a multistage, limiting lo amplifier. this results in consistent performance over a range of lo input power. optimum performance is achieved from ?6 dbm to +10 dbm, but the circuit continues to function at considerably lower levels of lo input power.
ADL5353 rev. 0 | page 17 of 24 the performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. this is a critical requirement in an interferer rich environ- ment, such as cellular infrastructure, where blocking interferers can limit mixer performance. the bandwidth of the intermodulation performance is somewhat influenced by the current in the lo amplifier chain. for dc current sensitive applications, it is per- missible to reduce the current in the lo amplifier by raising the value of the external bias control resistor. for dc current critical applications, the lo chain can operate with a supply voltage as low as 3.3 v, resulting in substantial dc power savings. in addition, when operating with supply voltages below 3.6 v, the ADL5353 has a power-down mode that permits the dc current to drop to <200 a. all of the logic inputs are designed to work with any logic family that provides a logic 0 input level of less than 0.4 v and a logic 1 input level that exceeds 1.4 v. all logic inputs are high impedance up to logic 1 levels of 3.3 v. at levels exceeding 3.3 v, protection circuitry permits operation of up to 5.5 v, although a small bias current is drawn. all pins, including the rf pins, are esd protected and have been tested to a level of 1500 v hbm and 500 v cdm.
ADL5353 rev. 0 | page 18 of 24 applications informa tion basic connections the ADL5353 mixer is designed to downconvert radio frequen - cies (rf) primarily between 22 00 mhz and 27 00 mhz to lower intermediat e fr equencies (if) between 30 mhz and 450 mhz. figure 51 depicts the basic connections of the mixer. t o prevent non zer o dc voltages from damaging the rf balun or lo input circuit, ac couple the rf and lo input port s. the rfin matching network consists of a series 1.5 pf capacitor and a shunt 10 nh inductor to provide the optimized rf input return loss for the desired frequency band if p ort . th e m ixer differential if interface requires pull - up choke inductors to bias the open - collector outputs and to set the output match . the shunting impedance of the choke inductors used to couple dc current into the if amplifier should be selected to provide the desired output return loss . the real part of the output impedance is ap proximately 200 ?, which match es many commonly used saw filters without the need for a transformer. this result s in a voltage conversion gain that is approximately 6 db higher than the power conversion gain , as show n in table 3 . when a 50 ? output impedance is needed , use a 4:1 impedance transformer , as shown in figure 51 . bias resistor select ion two external resistors, r bias if and r bia s lo , are used to adjust the bias curr ent of the integrated amplifiers at the if and lo terminals. it is necessary to have a sufficient amount of current to bias both the internal if and lo amplifiers to optimize dc current vs. optimum i ip3 performance. mixer vgs control da c the ADL5353 featu res two logic control pins , vgs0 (pin 12) and vgs1 ( pin 13) , that allow programmability for internal gate - to - source voltages for optimizing mixer performance over desired frequency bands. the evaluation board defaults both vgs0 and vgs1 to ground. 2 3 1 19 18 17 16 6 7 8 9 10 14 15 12 11 bias generator lo2 in rf in +5v +5v +5v +5v lo1 in 470nh 470nh if out +5v 100pf 10k? 10k? 10pf 10pf 10pf 1.5pf 10pf 0.1f 4.7f r bias lo r bias if 150pf 4:1 22pf 10pf 22pf ADL5353 20 13 5 4 09117-150 10nh figure 51 . typical application circuit
ADL5353 rev. 0 | page 19 of 24 evaluation board an evaluation board is available for the family of double balanced mixers. the standard evaluation board schematic is shown in figure 52 . the evaluation board is fabricated using rogers ? ro 3003 material . table 7 de scribes the various configuration options of the evaluation board. evaluation board layout is shown in figure 53 to figure 56. c22 1nf c20 10pf c2 10f c21 10pf c1 1.5pf c10 22pf c12 22pf vgs1 lo2_in lo1_in rf-in r22 10k ? v s pwr_up v s if1-out r23 15k ? v s v s v s losel vgs0 c5 0.01f c4 10pf c19 100pf c18 100pf c17 150pf r24 0? r25 0? l4 470nh l5 470nh c6 10pf c8 10pf r9 1.1k ? r4 10k ? r21 10k ? r1 0 ? r14 910 ? l3 0 ? t1 vpif rfin rfct comm comm vgs1 vpsw loi2 vgs0 loi1 ifon ifop ifgm pwdn lext vlo3 lgm3 vlo2 nc losw ADL5353 09117-151 z1 10nh figure 52 . evaluation board schematic
ADL5353 rev. 0 | page 20 of 24 table 7 . evaluation board configuration components function description default conditions c2, c6, c8, c18, c19, c20, c21 power supply decoupling nominal supply decoupling consists of a 10 f capacitor to ground in parallel with a 10 pf capacitor to ground positioned as close to the device as possible. c2 = 10 f (size 0603) c6, c8, c20, c21 = 10 pf (size 0402 ) c18, c19 = 100 pf (size 0402) c1, c4, c5 , z1 rf input interface the input channels are ac - coupled through c1. c4 and c5 provide bypassing for the center taps of the rf input baluns. c1 = 1.5 pf (size 0402) c4 = 10 pf (size 0402 ) c5 = 0.01 f (size 0402) z1 = 10 nh (size 0402) t1, c17, l4, l5, r1, r24, r25 if output interface the open - collector if output interfaces are biased through pull - up choke inductors , l4 and l5. t1 is a 4:1 impedance transformer used to provide a single - ended if outp ut interface , with c17 providing center - tap bypassing. remove r1 for balanced output operation. t1 = tc4 - 1w+ (mini - circuits ) c17 = 150 pf (size 0402) l4, l5 = 470 nh (size 1008) r1, r24, r25 = 0 ? (size 0402) c10, c12, r4 lo interface c10 an d c12 provide ac coupling for the lo1_in and lo2_in local oscillator inputs. losel selects the appropriate lo input for both mixer cores. r4 provides a pull - down to ensure that lo1_in is enabled when the losel test point is logic low. lo2_in is enabled whe n losel is pulled to logic high. c10, c12 = 22 pf (size 0402) r4 = 10 k ? (size 0402) r21 pwdn i nterface r21 pulls the pwdn logic low and enables the device. the pwr_up test point allows the pwdn interface to be exercised using the external logic gener ator. grounding the pwdn pin for nominal operation is allowed. using the pwdn pin when supply voltages exceed 3.3 v is not allowed. r21 = 10 k? (size 0402) c22, l3, r9, r14, r22, r23, vgs0, vgs1 bias c ontrol r22 and r23 form a voltage divider to provide 3 v for logic control, bypassed to ground through c22. vgs0 and vgs1 jumpers provide programmability at the vgs0 and vgs1 pins. it is recommended to pull these two pins to ground for nominal operation. r9 sets the bias point for the internal lo buffers. r14 sets the bias poin t for the internal if amplifier . c22 = 1 nf (size 0402) l3 = 0 ? (size 0603) r9 = 1.1 k ? (size 0402) r14 = 910 ? (size 0402) r22 = 10 k ? (size 0402) r23 = 15 k ? (size 0402) vgs0 = vgs1 = 3 - pin shunt
ADL5353 rev. 0 | page 21 of 24 09117-152 figure 53 . evaluation board top layer 09117-153 figure 54 . evaluation board ground plane, internal layer 1 09117-154 figure 55 . evaluation board power plane, internal layer 2 09117-155 figure 56 . evaluation board bottom layer
ADL5353 rev. 0 | page 22 of 24 outline dimensions compliant to jedec standards mo-220-vhhc 042209-b 1 0.65 bsc pin 1 indic at or 2.60 bsc 0.75 0.60 0. 50 top view 12 max sea ting plane pin 1 indic at or coplanarit y 0.05 0.90 0.85 0.80 0.35 0.28 0.23 0.05 max 0.01 nom 0.20 ref 0.70 0.65 0.60 3.20 3.10 sq 3.00 20 6 16 10 11 15 5 exposed pad (bottom view) 0.60 max 0.60 max 5.00 bsc sq 4.75 bsc sq for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 57 . 20 - lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp - 20 - 5) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering q uantit y ADL5353 a cpz -r7 ? 40c to +85c 20- lead lead frame chip scale package [lfcsp_vq] cp -20 -5 1,500 7 tape and reel ADL5353acpz - wp ? 40c to +85 c 20- lead lead frame chip scale package [lf csp_vq] cp -20 -5 36, waffle package ADL5353 - evalz evaluation board 1 1 z = rohs compli ant part.
ADL5353 r ev. 0 | page 23 of 24 notes
ADL5353 rev. 0 | page 24 of 24 notes ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09117 -0- 10/10(0)

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